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ÖVE/ÖNORM EN 16603-20-40

Issue date: 2024 06 15

Space engineering - ASIC, FPGA and IP Core engineering

This standard defines a comprehensive set of engineering requirements for the successful development of digital, analog and mixed analog-digital signal custom designed integrated circuits, such as application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) and Intellectual Property Cores (IP Cores), from now on referred to with the single and generic term DEVICEs. Microelectronics systems created by more than one DEVICE die but that are interconnected and packaged together as a system-in-package or multi-chip-module are not considered single monolithic DEVICEs, and therefore this kind of multi-die systems fall out of the scope of ECSS-E-ST-20-40. This standard can however be applied to the development of each individual monolithic die that can be integrated onto a larger multi-chip system, applying additional requirements. This standard may be tailored for the specific characteristic and constraints of a space project in conformance with ECSS-S-ST-00. A pre-tailoring based on the actual DEVICE type and criticality category of the DEVICE is addressed in clause 5.1.1.

General information on ÖVE/ÖNORM EN 16603-20-40

Format
Digital | 141 Pages
Language
English
Publisher
Austrian Standards International
Committee 237 Aerospace

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